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datasheet 74FCT38072S revision a 03/18/15 1 ?2015 integrated device technology, inc. low skew 1 to 2 clock buffer 74FCT38072S description the 74FCT38072S is a low skew, single input to two output, clock buffer. the 74FCT38072S ha s best in class additive phase jitter of sub 50 fsec. idt makes many non-pll and pll based low skew output devices as well as zero delay buffers to synchronize clocks. contact us for all of your clocking needs. features ? low additive phase jitter rms: 50fs ? extremely low skew outputs (50ps) ? low cost clock buffer ? packaged in 8-pin soic and 8-pin dfn, pb-free ? input/output clock frequency up to 200 mhz ? low power cmos technology ? operating voltages of 1.8v to 3.3v ? extended temperature range (-40 to +105c) block diagram q0 iclk q1
low skew 1 to 2 clock buffer 2 revision a 03/18/15 74FCT38072S datasheet pin assignments pin descriptions external components a minimum number of external components are required for prop er operation. a decoupling capacitor of 0.01 f should be connected between vdd pin and gnd pin, as close to the device as possible. a 33 ? series terminating resistor may be used on each clock output if the trace is longer than 1 inch. to achieve the low output skew that the 74FCT38072S is capable o f, careful attention must be paid to board layout. essentially, both outputs must have identical terminations, identical loads and identical trace geometries. if they do not, the output skew will be degraded. for example, using a 30 ? series termination on one output (with 33 ? on the others) will cause at least 15 ps of skew. pin number pin name pin type pin description 1 vdd power connect to +1.8v, +2.5 v, or +3.3 v. 2 vdd power connect to +1.8v, +2.5 v, or +3.3 v. 3 iclk input clock input. 4 gnd power connect to ground. 5 gnd power connect to ground. 6 q0 output clock output 0. 7 q1 output clock output 1. 8 gnd power connect to ground. 1 2 3 vdd 4 q0 q1 gnd iclk 8 7 6 5 8-pin soic vdd gnd gnd 1 2 3 vdd 4 q0 q1 gnd iclk 8 7 6 5 8-pin dfn gnd gnd vdd
revision a 03/18/15 3 low skew 1 to 2 clock buffer 74FCT38072S datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent da mage to the 74FCT38072S. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functi onal operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect pr oduct reliability. electrical paramete rs are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 3.465v outputs -0.5 v to vdd+0.5 v iclk 3.465v ambient operating temperature (extended) -40 to +105 ? c storage temperature -65 to +150 ? c junction temperature 125 ? c soldering temperature 260 ? c parameter min. typ. max. units ambient operating temperature (extended) -40 +105 ? c power supply voltage (measured in respect to gnd) +1.71 +3.465 v
low skew 1 to 2 clock buffer 4 revision a 03/18/15 74FCT38072S datasheet dc electrical characteristics (vdd = 1.8v, 2.5v, 3.3v) vdd=1.8v 5% , ambient temperature -40 to +105c, unless stated otherwise notes: 1. nominal switching threshold is vdd/2 vdd=2.5 v 5% , ambient temperature -40 to +105c, unless stated otherwise vdd=3.3 v 5% , ambient temperature -40 to +105c, unless stated otherwise parameter symbol conditions min. typ. max. units operating voltage vdd 1.71 1.89 v input high voltage, iclk v ih note 1 0.7xvdd vdd v input low voltage, iclk v il note 1 0.3xvdd v output high voltage v oh i oh = -10 ma 1.3 v output low voltage v ol i ol = 10ma 0.35 v operating supply current idd no load, 135 mhz 15 ma nominal output impedance z o 17 ? input capacitance c in iclk 5 pf parameter symbol conditions min. typ. max. units operating voltage vdd 2.375 2.625 v input high voltage, iclk v ih note 1 0.7xvdd vdd v input low voltage, iclk v il note 1 0.3xvdd v output high voltage v oh i oh = -16 ma 1.8 v output low voltage v ol i ol = 16 ma 0.5 v operating supply current idd no load, 135 mhz 18 ma nominal output impedance z o 17 ? input capacitance c in iclk 5 pf parameter symbol conditions min. typ. max. units operating voltage vdd 3.15 3.45 v input high voltage, iclk v ih note 1 0.7xvdd vdd v input low voltage, iclk v il note 1 0.3xvdd v output high voltage v oh i oh = -25 ma 2.2 v output low voltage v ol i ol = 25 ma 0.7 v operating supply current idd no load, 135 mhz 22 ma nominal output impedance z o 17 ? input capacitance c in iclk 5 pf
revision a 03/18/15 5 low skew 1 to 2 clock buffer 74FCT38072S datasheet ac electrical characteristics (vdd = 1.8v, 2.5v, 3.3v) vdd = 1.8v 5% , ambient temperature -40 to +105c, unless stated otherwise vdd = 2.5 v 5% , ambient temperature -40 to +105c, unless stated otherwise vdd = 3.3 v 5% , ambient temperature -40 to +105c, unless stated otherwise notes: 1. with rail to rail input clock 2. between any 2 outputs with equal loading. 3. duty cycle on outputs will match incoming clock dut y cycle. consult idt for tigh t duty cycle clock generators. parameter symbol conditions min. typ. max. units input frequency 0200mhz output rise time t or 0.36 to 1.44 v, c l =5 pf 0.6 1.0 ns output fall time t of 1.44 to 0.36 v, c l =5 pf 0.6 1.0 ns start-up time t start-up part start-up time for valid outputs after vdd ramp-up 2ms propagation delay note 1 1.5 2.5 4 ns buffer additive phase jitter, rms 125mhz, integration range: 12khz-20mhz 0.05 ps output to output skew rising edges at vdd/2, note 2 50 65 ps device to device skew rising edges at vdd/2 200 ps parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.5 to 2.0 v, c l =5 pf 0.6 1.0 ns output fall time t of 2.0 to 0.5 v, c l =5 pf 0.6 1.0 ns start-up time t start-up part start-up time for valid outputs after vdd ramp-up 2ms propagation delay note 1 1.8 2.5 4.5 ns buffer additive phase jitter, rms 125mhz, integration range: 12khz-20mhz 0.05 ps output to output skew rising edges at vdd/2, note 2 50 65 ps device to device skew rising edges at vdd/2 200 ps parameter symbol conditions min. typ. max. units input frequency 0 200 mhz output rise time t or 0.66 to 2.64 v, c l =5 pf 0.6 1.0 ns output fall time t of 2.64 to 0.66 v, c l =5 pf 0.6 1.0 ns start-up time t start-up part start-up time for valid outputs after vdd ramp-up 2ms propagation delay note 1 1.5 2.5 4 ns buffer additive phase jitter, rms 125mhz, integration range: 12khz-20mhz 0.05 ps output to output skew rising edges at vdd/2, note 2 50 65 ps device to device skew rising edges at vdd/2 200 ps
low skew 1 to 2 clock buffer 6 revision a 03/18/15 74FCT38072S datasheet test load and circuit thermal characteristics (8soic) marking diagrams notes: 1. ? ** ? is the lot number. 2. ?yyww? or ?yw? are the last digits of th e year and week that the part was assembled. 3 ?g? denotes rohs compliant package. 4. ?$? denotes the mark code. 5. ?i? denotes extended temperature range device. parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 150 ? c/w ? ja 1 m/s air flow 140 ? c/w ? ja 3 m/s air flow 120 ? c/w thermal resist ance junction to case ? jc 40 ? c/w rs=33ohm 5 i n c h e s cl = 5pf 50ohms 072s yw** 8-pin dfn idt74fc t38072s dcgi yyww$ 8-pin soic
revision a 03/18/15 7 low skew 1 to 2 clock buffer 74FCT38072S datasheet package outline and package dimensions (8-pin dfn, 2mm x 2 mm body, 0.5mm pitch)
low skew 1 to 2 clock buffer 8 revision a 03/18/15 74FCT38072S datasheet package outline and pack age dimensions, cont. (8-pin dfn, 2mm x 2mm body, 0.5mm pitch)
revision a 03/18/15 9 low skew 1 to 2 clock buffer 74FCT38072S datasheet package outline and package dimensions (8-pin soic, 150 mil. narrow body) ordering information ?g? after the two-letter package code denotes pb-free configuration, rohs compliant. part / order number marking shippi ng packaging package temperature 74FCT38072Sdcgi see page 6 tubes 8-pin soic -40 to +105 ? c 74FCT38072Sdcgi8 tape and reel 8-pin soic -40 to +105 ? c 74FCT38072Scmgi cut tape 8-pin dfn -40 to +105 ? c 74FCT38072Scmgi8 tape and reel 8-pin dfn -40 to +105 ? c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c ? c l h h x 45 *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 a0 ? 8 ? 0 ? 8 ?
low skew 1 to 2 clock buffer 10 revision a 03/18/15 74FCT38072S datasheet revision history rev. date originator description of change a 03/18/15 b. chandhoke initial release.
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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